1. Field of the Invention
This invention relates generally to processor-based systems, and, more particularly, to saving and restoring soft repair data in a processor-based system.
2. Description of the Related Art
Processor cores typically include cache arrays or macros for storing information that defines the current state of the processor core. The cache arrays are formed of numerous rows and columns of memory elements. Although the memory elements that make up the cache arrays are generally very reliable, they are not perfectly reliable and they can in some instances fail. Failure may be the result of defects or errors during fabrication of the cache arrays or may be the result of portions of the cache array wearing out or malfunctioning over time. A failed cache array or macro can severely impact the operation of the processor core and so processor cores often implement various techniques for recovering from cache array or macro failures. One approach is to include redundant portions of the cache arrays, such as one or more redundant rows and/or columns of memory elements that can be used in place of a failed row and/or column.
A memory built-in self test (MBIST) can be used to detect failures in the cache arrays of a processor core. For example, the MBIST can be run during a cold reset of the processor core. When the MBIST detects a failure in a portion of a cache array, such as a column of the cache array, the MBIST can repair the failed column by performing a hard repair using hardware fuses. Hard repair is typically targeted for cache failures found at the time of product testing at the manufacturer. To implement a hard repair, selected hardware fuses are blown to effect changes in the physical connections within the macros so that the failed column is operationally replaced with one of the redundant columns. For example, the MBIST can communicate with a fuse slave controller that is configured to blow the appropriate fuses to replace the failed column with one of the redundant columns. The area available in the core for hardware elements is very limited and consequently the number of fuses available within the processor core is limited to a number that is typically significantly less than the number that would be required to utilize all of the redundant columns using fuses.
The MBIST can also use soft repair techniques to repair failed cache arrays using redundant hardware. Soft repair is typically used to address failures in the field and/or with the end-user because of variations of the operating conditions like temperature. To implement a soft repair, the processor core includes a bank of registers that includes information that can be used to repair failed cache arrays. For example, when the MBIST detects an error or failure in a column of a cache array, the fuse slave controller generates information that can be used to modify the operation of the cache array so that the redundant columns are used in place of the failed column. Soft repairs do not change the physical structure of the array. This information is stored in the registers so that it can be read by the microcode that controls operation of the cache array. The registers including the soft repair information are erased when the processor core is powered down (or power gated) and so conventional processor cores run an MBIST when the core is powered up to regenerate the soft repair information. Re-creating the soft repair information by running an MBIST increases the latency of the power-up procedure.